1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a delay time controlling circuit of a semiconductor memory device, which is capable of controlling delay time and a method for controlling delay time.
2. Description of the Related Art
As integration density and operational speed of semiconductor memory devices increases, operational cycles inside a chip become faster, and accordingly, it becomes more difficult to control a skew of internal signals. Conventional semiconductor memory devices are typically tested before encapsulation in a carrier package (i.e., while in a wafer state) and produce test results that are equivalent to the results of testing a semiconductor memory device which is completely packaged.
However, in recently-developed semiconductor memory devices, new interface logic having higher operating speeds may include a delay locked loop (DLL) or a phase locked loop (PLL), circuit for compensating a clock skew. Since a test circuit for such memory devices may operate at a speed of about 100-250 MHz, it is typically manufactured to optimally test only the memory devices. Such optimization makes it is impossible to accurately test the operational characteristics of an interface logic circuit, a DLL circuit, or a PLL circuit with such a memory test circuit while a semiconductor memory device remains in a wafer state. Further, electrical signals in a semiconductor memory device operating at a speed of several hundred mega bytes per second may be significantly effected by parasitic impedances associated with a particular set of packaging properties, thus invalidating test measurements of the memory device wafer unless it is encapsulated in a finished product package. Since a sealed and packaged chip is very difficult to access, control of internal signals and test points makes accurate device testing possible only by using repeated trial and error methods, thereby increasing the manufacturing cost and lengthening processing time.
FIG. 1 illustrates a circuit diagram of a conventional delay-time controlling circuit 100 in a semiconductor memory device, which includes a variable delay line (VDL) 101, a fuse unit 103, and a pair of inverters 105 and 107.
Delay time controlling circuit 100 controls delay time in response to a digital input signal (m) derived from a selective cutting of particular fuses in fuse unit 103. In other words, in order to create a particular delay in a semiconductor memory device, the selected fuses in the fuse unit 103 are cut, thereby allowing the variable delay line (VDL) 101 and thence delay time controlling circuit 100 to delay signals in the semiconductor memory device. If no delay is needed in the semiconductor memory device, the fuses are not cut.
Disadvantageously, since the selected fuses are typically cut when the semiconductor memory device is still in a wafer state, associated wafer level testing cannot ensure accurate delay-time characteristics of the finished semiconductor memory device due to the electrical characteristics associated with the missing package.
As described above, the conventional delay time controlling circuit of a semiconductor memory device controls delay time under a condition wherein the semiconductor memory device is in a wafer state and not yet packaged. Accordingly, the characteristics of the semiconductor memory device may change after being packaged, in which case additional processes are required to accurately control any delay times, thereby increasing the manufacturing cost and processing time of semiconductor memory devices.
To solve the above-described problems, it is a first feature of an embodiment of the present invention to provide a delay time controlling circuit in a semiconductor memory device, which is capable of controlling a delay time of the semiconductor memory device after the semiconductor memory device has been completely encapsulated in a finished package. This setting of a delay time is preferably performed without the need of additional processes.
It is a second feature of the present invention to provide a method for controlling the delay time in a packaged semiconductor memory device.
A delay time controlling circuit according to a first embodiment of the present invention preferably includes: a programmable variable delay circuit, a controller, a fuse unit having electric fuses, a selection fuse, and a selector, which may be a multiplexer. The controller, which includes a register for storing data, generates a first code signal, which is an m-bit signal (where m is a natural number) in response to a first control signal, which is routed to the programmable variable delay circuit, thereby introducing a programmed time delay into an input signal. The fuse unit also receives the first code signal, cuts selected included fuses in response to a second control signal when a measured delay time reaches a target delay time, and generates a second code signal, which is an m-bit signal (where m is a natural number)that corresponds to the logic value of the fuses that are cut. The selection fuse is cut in response to a third control signal either simultaneously with or after the selected fuses in the fuse unit are cut. The selector selects one of the first and second code signals based on whether or not the selection fuse is cut and outputs the selected signal as a delay control signal for controlling the delay time of the programmable variable delay circuit. The first, second and third control signals may be generated externally to the time delaying circuit, and the second and third control signals may be the same signal.
A delay time controlling circuit according to a second embodiment of the present invention preferably includes a programmable variable delay circuit, a phase detector, a controller, a fuse unit having electric fuses, a selection fuse, and a selector, which may be a multiplexer. The phase detector compares the phase of a reference signal and the phase of an output signal of the programmable variable delay circuit in response to an enabling first control signal and generates a code control signal (based on the results of the comparison). The controller, which preferably has a register for storing and outputting a predetermined logic code, generates a first code signal, which is an m-bit signal (where m is a natural number) in response to the code control signal, which is routed to the programmable variable delay circuit, thereby introducing a programmed time delay into an input signal. The fuse unit also receives the first code signal, cuts fuses in itself in response to the second control signal if the measured delay time reaches a target delay time (i.e., the phase difference becomes zero,) and generates a second code signal, which is an m-bit signal (where m is a natural number) and corresponds to the logic value of the fuses that are cut. The selection fuse is cut in response to a third control signal. The selector selects one of the first and second code signals based on whether or not the selection fuse is cut and outputs the selected code signal as a delay control signal for controlling the delay time of the programmable variable delay circuit. Here, the code control signal controls the logic code of the controller based on the difference in phase between the reference signal and the output signal of the variable delay circuit. The second and third control signals may be generated internally or applied externally to the time delay controlling circuit and may be the same signal.
To achieve the second feature, there is provided a first method for controlling the delay time of a delay time controlling circuit according to the first embodiment of the present invention. The first method preferably includes (a) outputting a first code signal which is an m-bit signal (where m is a natural number) in response to a first control signal (which may also be an m-bit signal) (b) controlling and measuring the delay time of the programmable variable delay circuit in response to the first code signal, (c) cutting fuses in a fuse unit in response to a second control signal if the measured delay time reaches a target delay time and generating a second code signal which is an m-bit signal (where m is a natural number) and corresponds to the logic value of the fuses that are cut, and (d) outputting the second code signal as a delay control signal and thus fixing the delay time of the programmable variable delay circuit. The first and second control signals may be generated internally or applied externally to the time delay controlling circuit
There is also provided a second method for controlling the delay time of a delay time controlling circuit according to the second embodiment of the present invention. The method preferably includes (a) comparing the phase of a reference signal which is an m-bit signal (where m is a natural number) and the phase of an output signal of the programmable variable delay circuit in response to a first control signal and generating a code control signal based on the results of the comparison, (b) generating a first code signal which is an m-bit signal (where m is a natural number) in response to the code control signal, (c) controlling and measuring delay time of the variable delay circuit in response to the first code signal, (d) cutting fuses in a fuse unit in response to a second control signal if the measured delay time reaches a target delay time and generating a second code signal which is an m-bit signal (where m is a natural number) and corresponds to the logic value of the fuses that are cut, and (e) outputting the second code signal as a delay control signal and thus fixing the delay time of the programmable variable delay circuit. Preferably, the code control signal controls the logic code of the first code signal based on the difference in phase between the reference signal and the output signal of the variable delay circuit
Preferably, the delay time controlling circuit and the method for controlling delay time are capable of controlling the delay time of a semiconductor memory device after the semiconductor memory device has been completely packaged without the need of additional processes.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.